The present invention relates to a liquid crystal drive circuit for outputting a voltage for driving a liquid crystal, and a liquid crystal display system including the circuit.
As a device which selects one of four different voltages V1 to V4 for driving a liquid crystal panel and outputs the selected voltage, and to which the present invention pertains, the device shown in FIG. 8 is known. This device comprises, e.g., 160 blocks BL1 to BL160 each including a shift register unit 111 for shifting an input signal IN, an output selection circuit 112 for determining the voltage to be output to the liquid crystal panel, and an output buffer 113 for outputting the voltage determined by the output selection circuit 112.
The shift register unit 111 has a shift register including an inverter IN51 for receiving a clock CLK and outputting an inverted clock /CLK, clocked inverters CIN51 to CIN54 which are enabled/disabled in response to the input clocks CLK and /CLK, and inverters IN52 and IN53. When the clocked inverter CIN51 is enabled in response to the clock CLK, the input signal IN is inverted and output. When the clocked inverter CIN51 is disabled, the clocked inverter CIN53 is enabled to hold the output state of the inverter IN52. This output is inverted by the clocked inverter CIN52, and is inverted again by the inverter IN53. When the clocked inverter CIN52 is disabled, the clocked inverter CIN54 is enabled to hold the output form the inverter IN53. The output from the inverter IN53 is supplied to the output selection circuit 112 as an output signal Q1 of the shift register unit 111.
The output selection circuit 112 receives the output signal Q1 from the shift register unit 111, and a frame signal FR, the level of which is inverted in units of frames. Two-input NAND gates NA61 to NA64 receive one of the frame signal FR and its inverted signal /FR obtained via an inverter IN71, and one of the output from the shift register unit 111 and its inverted signal obtained via an inverter IN72, and respectively supply their outputs to the output buffer 113 as switching control signals SELL to SEL4.
The output buffer 113 receives four different voltages V1 to V4, and the switching control signals SEL1 to SEL4 output from the output selection circuit 112, and selects and outputs one voltage to be supplied to a liquid crystal panel (not shown) on the basis of the signals SEL1 to SEL4. The switching control signals SEL1 to SEL4, and signals /SEL1 to /SEL4 respectively inverted by inverters IN61 to IN64 are supplied to switching elements SW61 to SW64 each constituted by a combination of p- and n-MOS transistors to turn on one of these switching elements. In this way, the selected one of the four voltages V1 to V4 is output as an output voltage OUT1.
In other blocks BL2 to BL160 as well, the shift register units 111 generate signals Q2 to Q160, and supply them to the output selection circuits 112. The output selection circuits 112 output switching signals SEL1 to SEL4, and the output buffers 113 output the selected voltages. Note that the signals Q1 to S160 in the shift register units 111 in the blocks BL1 to BL160 have shifts toward the latter stages.
The voltages V1 to V4 are generated by a power supply circuit shown in FIG. 9. A predetermined power supply voltage V.sub.DD and ground voltage V.sub.ss are supplied to a DC-DC converter 101 to generate a voltage V.sub.GG. The voltage V.sub.GG is input to an emitter-follower circuit including a resistor 102, variable resistor 108, and a pnp bipolar transistor 113 to output a voltage V.sub.EE. The potential difference between the voltages V.sub.GG and V.sub.EE is divided by the resistances of five fixed resistors 103 to 107, and four sets of operational amplifiers 109 to 112, resistors 114 to 117, and capacitors 118 to 121 output stabilized voltages V1 to V4.
However, the liquid crystal drive circuit shown in FIG. 8 suffers the following problems. After the power supply is turned on and the power supply voltage stabilizes, data is input from a terminal IN, and the clock CLK is input from a clock terminal CLK. Then, the shift register units 111 are enabled to shift the data, and the values of the output signals Q1 to Q160 of the shift register units of all the blocks are determined. A long period of time is required from when the power supply is turned on until the values of the signals Q1 to Q160 are determined, and the signal values remain unknown during this interval. For this reason, whether or not the liquid crystal panel applied with one of the voltages V1 to V4 at its scanning electrodes is turned on is finally uncertain.
If the liquid crystal panel is turned on upon power ON, electric power is wasted during this interval. Furthermore, since an unnecessary current path is formed in the power supply circuit shown in FIG. 9 in this case, the rise time required until the power supply voltage reaches a prescribed level is prolonged. As described above, the liquid crystal drive circuit shown in FIG. 8 suffers the problems including an increase in consumption power and a decrease in display response speed of the liquid crystal panel.